The present invention relates to a multi-phase clock generator circuit, and more particularly to a clock generator circuit having a phase lock loop for generating a plurality of synchronizing clock signals.
It had been known in the art to which the invention pertains that the phase lock loop is used for generating multi-phase internal clock signals from an external clock signal.
FIG. 1A is a circuit diagram illustrative of a conventional clock generator circuit having a phase lock loop. The clock generator circuit has a phase lock loop circuit 1A which receives an input of clock signals CL and generates an output of clock signals CAA which frequency is four times higher than the clock signals CL. The clock generator circuit also has 1/2 frequency divider circuit 2A which receives an input of the clock signals CAA and generates an output of clock signals CBA which is lower by two times than the clock signals CAA. The clock generator circuit also has logic circuits for generating two phase internal clock signals C1 and C2. The logic circuit has first and second AND gates 11 and 12 as well as first and second delay circuits 7 and 8 in addition an invertor circuit 13. The first AND circuit 11 has an output side which is connected to a first output terminal on which the first internal clock signal C1 appears. The second AND circuit 12 has an output side which is connected to a second output terminal on which the second internal clock signal C2 appears. The output side of the first AND circuit 11 is also connected to an input side of the second delay circuit 8. The output side of the second AND circuit 12 is also connected to an input side of the first delay circuit 7. The first delay circuit generates from the output side a delayed signal C7. The output side of the first delay circuit 7 is connected to one of the input terminals of the first AND gate 11. The output side of the 1/2 frequency divider circuit 2A is also connected to another input terminal of the first AND gate 11. The second delay circuit 8 generates from the output side a second delayed signal C8. The output side of the second delay circuit 8 is connected to one of the input terminals of the second AND gate 12. The output side of the 1/2 frequency divider circuit 2A is also connected to an input side of the invertor 13. The invertor 13 generates from an output side an inverted signal. The output side of the invertor 13 is connected to one of the input terminals of the second AND gate 12. The output side of the second delay circuit 8 is connected to the other input terminal of the second AND gate 12.
FIG. 1B is a circuit diagram illustrative of a first delay circuit provided in a conventional clock generator circuit having a phase lock loop of FIG. 1A. The first delay circuit 7 comprises a resistor R1 connected in series between the input and output sides, and a capacitor C1 connected between a ground line and the output side of the first delay circuit 7.
FIG. 1C is a circuit diagram illustrative of a second delay circuit provided in a conventional clock generator circuit having a phase lock loop of FIG. 1A. The second delay circuit 8 comprises a series connection of two invertor circuits 17 and 18 between the input and output sides as well as a capacitor C2 connected between the ground line and an intermediate point between the two invertor circuits 17 and 18. The invertor circuit 17 is connected to the input side whilst the invertor circuit 18 is connected to the output side.
FIG. 2 is a timing chart illustrative of waveforms of lock signals transmitting in a conventional clock generator circuit of FIG. 1A. The clock signal C1 is inputted into the phase lock loop circuit 1A whereby the external clock signal C1 is fourfold-multiplied to generate the signal CAA which is four times higher in frequency than the clock signal C1. The signal CAA is then inputted into the 1/2 frequency divider circuit 2A whereby the signal CAA is divided to generate the signal CBA. The first internal clock signal C1 falls in synchronization with the fall-timing of the signal CBA and rises in synchronous with the fall-timing of the first delayed signal C7 which is delayed by a time period TD1A from the fall-timing of the second internal clock C2. The second internal clock signal C2 fall in synchronization with the rise-timing of the signal CBA and rises in synchronization with the fall-timing of the second delayed signal C8 which is delayed by the time period TD1A from the fall-timing of the first internal clock C1. If the multiple phase internal clock signals are used, it is required to avoid any overlap of high level time periods of the multiple phase internal clock signals, for which purposes the first and second delay circuits 7 and 8 are provided to delay the rise-timings of the first and second internal clock signals C1 and C2.
The above conventional clock generator circuit has the following problems related to the first and second delay circuits 7 and 8. Variations in conditions for semiconductor manufacturing processes cause variations in the resistance value of the resistor R1 used in the first delay circuit 7 as well as variation in capacitance of the capacitors C1 and C2 used in the first delay circuit 7. Such variations can also cause variation in trans conductance of transistors used in the investors 17 and 18 of the second delay circuit 8. Furthermore, the resistance value of the resistor R1 and the trans conductance of transistors used in the invertors 17 and 18 are variable depending upon a temperature of the transistors in use. Moreover the trans conductance of transistors used in the invertors 17 and 18 is variable depending upon a power voltage for driving the circuit. A total amount of the variation in those parameters may be considerable. Considering that the total amount of the variation in those parameters has a maximum value, then the delayed time of the delay circuit may be varied by 50% or more. Such large variation in delay time of the delay circuit causes a large variation in duty of the first and second internal clock signals C1 and C2. This makes it difficult to set wide operational conditions of the semiconductor device.
In the above circumstances, it had been required to develop a novel multi-phase clock generator circuit with reduced variation in duty of internal clock signals.